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    <title>DSpace Collection:</title>
    <link>http://hdl.handle.net/2268.2/6042</link>
    <description />
    <pubDate>Mon, 07 Sep 2026 09:00:49 GMT</pubDate>
    <dc:date>2026-09-07T09:00:49Z</dc:date>
    <item>
      <title>Master thesis : Hardware and Software Development of a Custom Collimated Multi-Wavelength UV Light Source for MSLA 3D Printing</title>
      <link>http://hdl.handle.net/2268.2/26095</link>
      <description>Title: Master thesis : Hardware and Software Development of a Custom Collimated Multi-Wavelength UV Light Source for MSLA 3D Printing
Abstract: Masked stereolithography apparatus (MSLA) 3D printing relies on the selective transmission of ultraviolet light through an LCD screen to cure photosensitive resins layer by layer. In this process, the illumination system has a direct influence on the achievable irradiance, exposure uniformity, optical bleeding, and resin compatibility. This work focuses on the development of a custom collimated multi-wavelength UV source for an experimental MSLA printer developed within the Microsys laboratory.&#xD;
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The proposed source operates at 365 nm, 385 nm, and 405 nm, with the objective of extending the range of usable photopolymer resins and investigating the influence of wavelength on pixel-scale optical spreading. The work includes the characterization of existing illumination systems, the study of LED–lens alignment effects, the selection of UV LEDs and collimation optics, and the comparison of two source architectures. Dedicated electronic boards were designed and tested to drive the high-power LEDs, select the active wavelength, and integrate the source into the printer electronics.&#xD;
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The developed hardware was validated electrically and thermally, and a partial optical prototype was characterized experimentally. The measurements showed that the source can produce collimated illumination with an estimated half-beam angle of approximately 3.5°. With a six-lens prototype, the maximum irradiance measured after the LCD reached 1.58 mW/cm² at 365 nm, 4.26 mW/cm² at 385 nm, and 5.23 mW/cm² at 405 nm. The 405 nm value is comparable to the irradiance of the previous single-wavelength source used in the printer. Simulations of the complete source indicate that the dense Parmigiana LED1 architecture should provide the best compromise between irradiance and uniformity.&#xD;
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The experiments also highlighted several limitations of the present setup. In particular, the current RGB LCD screen exhibits low UV transmittance, especially at shorter wavelengths, and the irradiance pattern transmitted through a red sub-pixel was found to be much wider than the physical aperture. Although a reduction of this spreading was expected at shorter wavelengths, it was not observed under the tested conditions.</description>
      <pubDate>Sun, 28 Jun 2026 22:00:00 GMT</pubDate>
      <guid isPermaLink="false">http://hdl.handle.net/2268.2/26095</guid>
      <dc:date>2026-06-28T22:00:00Z</dc:date>
    </item>
    <item>
      <title>Master thesis : FMCW Radar Prototyping for Proximity-Sensing Applications</title>
      <link>http://hdl.handle.net/2268.2/26093</link>
      <description>Title: Master thesis : FMCW Radar Prototyping for Proximity-Sensing Applications
Abstract: This master thesis studied the design, implementation and experimental validation of a FMCW radar prototype for proximity-fuze applications. The goal was to evaluate the feasibility of a short range radar chain able to detect targets under the constraints of high relative velocity, short ranges and compact hardware integration.&#xD;
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The work first presents radar techniques for proximity sensing, focusing on FMCW operation and its limitations in high-Doppler scenarios. The theoretical constraints related to chirp duration, beat-signal bandwidth, sampling frequency, and range-Doppler coupling are then analysed in order to identify realistic operating conditions for the developed 5.5 GHz prototype. An RF front-end is combined with an acquisition board based on an STM32H7 microcontroller. This board handles power distribution, analog signal conditioning, and digital signal processing for target range estimation.&#xD;
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The results confirmed the correct operation of the FMCW chain and the detection of a moving metallic reflector with the radar prototype. Due to hardware constraints, the FSK approach was explored in order to evaluate an alternative suitable to compact integration, while still allowing both range and velocity tracking of a target.; Ce travail de fin d'études étudie la conception, la réalisation et la validation expérimentale d’un prototype de radar FMCW destiné à des applications de détonateur de proximité. L'objectif était d'évaluer la faisabilité d'une chaîne radar courte portée capable de détecter des cibles dans des conditions contraintes par une vitesse relative élevée, ainsi qu'une intégration matérielle compacte.&#xD;
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Le travail présente d'abord les techniques radar pour la détection de proximité, en mettant l'accent sur le fonctionnement FMCW et sur ses limites dans les situations à fort effet Doppler. Les contraintes théoriques liées à la durée des chirps, à la bande passante du signal de battement, à la fréquence d'échantillonnage et au couplage distance-Doppler sont ensuite analysées afin d'identifier des conditions de fonctionnement réalistes pour le prototype à 5,5 GHz développé. Un front-end RF est associé à une carte d'acquisition basée sur un microcontrôleur STM32H7. Cette carte prend en charge la distribution de l'alimentation, le conditionnement analogique des signaux ainsi que leur traitement numérique, permettant ainsi l'estimation de la distance à la cible.&#xD;
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Les résultats ont confirmé le fonctionnement de la chaîne FMCW, la détection d'un réflecteur métallique mobile avec le prototype radar. En raison des contraintes matérielles, l'approche FSK a ensuite été explorée afin d’évaluer une alternative plus adaptée à l'implémentation embarquée, permettant le suivi en distance et vitesse d'une cible.</description>
      <pubDate>Sun, 28 Jun 2026 22:00:00 GMT</pubDate>
      <guid isPermaLink="false">http://hdl.handle.net/2268.2/26093</guid>
      <dc:date>2026-06-28T22:00:00Z</dc:date>
    </item>
    <item>
      <title>Master thesis : Cell-Free Massive MIMO with Dynamic Metasurface Antennas: Uplink Resource Allocation under Max-Min Fairness</title>
      <link>http://hdl.handle.net/2268.2/26091</link>
      <description>Title: Master thesis : Cell-Free Massive MIMO with Dynamic Metasurface Antennas: Uplink Resource Allocation under Max-Min Fairness
Abstract: Cell-Free massive MIMO is a promising architecture for future wireless networks. Instead of relying on a single base station, it distributes many Access Points (APs) across the coverage area and serves all users jointly, eliminating the coverage problems that arise at cell edges. Deploying cell-free, however, requires a massive number of APs, each equipped with multiple antennas, which leads to considerable hardware complexity and energy consumption. In particular, conventional fully-digital architectures, which assign one Radio-Frequency (RF) chain per antenna element, quickly become prohibitively costly and power-hungry.&#xD;
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Dynamic Metasurface Antennas (DMAs) directly address this problem. A DMA performs analog beamforming through tunable metamaterial elements embedded in waveguides. A single RF chain can drive a large number of radiating elements simultaneously. This significantly reduces both hardware complexity and power consumption compared to fully-digital or hybrid architectures, making DMAs well suited for large-scale deployments.&#xD;
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This thesis investigates the use of DMAs as AP hardware in a Cell-Free massive MIMO network. The first part builds the necessary background: the electromagnetic behavior of DMA elements is characterized through the Lorentzian resonance model, which inherently couples the phase and amplitude of each element and constitutes the central hardware constraint of this work. &#xD;
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The second part addresses the uplink problem under a max-min Signal-to-Interference-plus-&#xD;
Noise Ratio (SINR) fairness criterion for DMA-enhanced Cell-Free MIMO, ensuring uniform Quality of Service (QoS) across all users. The resulting optimization problem involves three coupled sets of variables: digital combining vectors, per-user transmit powers, and DMA weight matrices. To solve this non-convex problem, an alternating optimization framework is developed. Within this framework, two algorithms are proposed for updating the DMA weights: one based on Semidefinite relaxation (SDR) and another based on gradient-ascent (GA) over the Lorentzian phase parameters.&#xD;
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Simulations in an Indoor Factory environment show that both algorithms achieve a 6–8 dB gain over an unoptimized baseline and stay within 2.5–4 dB of the fully-digital upper bound. Distributing antennas across multiple access points consistently improves the worst-user SINR, confirming the macro-diversity benefit of the Cell-Free architecture. Overall, these results demonstrate that DMA-based Cell-Free Massive MIMO constitutes a practical, cost-effective, and energy-efficient solution for next-generation industrial wireless systems.</description>
      <pubDate>Sun, 28 Jun 2026 22:00:00 GMT</pubDate>
      <guid isPermaLink="false">http://hdl.handle.net/2268.2/26091</guid>
      <dc:date>2026-06-28T22:00:00Z</dc:date>
    </item>
    <item>
      <title>Master thesis : SMPTE ST 2110 Stream Analyzer</title>
      <link>http://hdl.handle.net/2268.2/26088</link>
      <description>Title: Master thesis : SMPTE ST 2110 Stream Analyzer
Abstract: The broadcast industry is transitioning from Serial Digital Interface, SDI, systems to an uncompressed IP-based architecture because of the necessity to have more flexibility and scalability of the networks. The SMPTE ST 2110 standards have emerged to guide this transition and define how uncompressed media, such as video, audio and ancillary data, is carried over an IP network.&#xD;
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While IP networks do offer multiple advantages, they come with their own challenges, specifically in terms of timing and network jitter as well as possible buffer congestion. Commercial analyzers for these streams do exist but they operate as black boxes and cannot be integrated into custom hardware. Thus, this thesis presents the design and implementation of an SMPTE ST 2110 stream analyzer implemented on an FPGA and developed at Deltatec.&#xD;
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The SMPTE ST 2110 stream analyzer uses a hardware and software co-design that allows the FPGA to monitor high-speed streams, with the visualization being done with a Python interface.&#xD;
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This analyzer is comprised of four modules. The  Packet Interval Time, PIT, analyzer measures the difference in time between packet arrivals and outputs an animation of the minimum, maximum, and average over time, as well as a PIT histogram. The Virtual Receiver buffer, VRX, analyzer implements the SMPTE ST 2110-21 virtual receiver buffer and outputs the buffer level's minimum, maximum, and average over time to ensure that the buffer is not dealing with any overflows or underflows. &#xD;
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The Network Compatibility model, C, analyzer observes the sender's traffic shaping against the actual network compatibility model in order to ensure that Ethernet switch buffers do not overflow. The RTP stream analyzer monitors redundant streams to decide which receiver class they should belong to and whether the packets are coming too far out of order.</description>
      <pubDate>Sun, 28 Jun 2026 22:00:00 GMT</pubDate>
      <guid isPermaLink="false">http://hdl.handle.net/2268.2/26088</guid>
      <dc:date>2026-06-28T22:00:00Z</dc:date>
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