Master thesis : Characterization of the performance of an analog Image acquisition chain using a custom-made automated test bench
Promotor(s) : Vanderbemden, Philippe
Date of defense : 26-Jun-2019/27-Jun-2019 • Permalink :
|Title :||Master thesis : Characterization of the performance of an analog Image acquisition chain using a custom-made automated test bench|
|Author :||Grodent, Antoine|
|Date of defense :||26-Jun-2019/27-Jun-2019|
|Advisor(s) :||Vanderbemden, Philippe|
|Committee's member(s) :||Brixhe, Lionel
|Keywords :||[en] ADC|
[en] Input referred noise
[en] Differential Non Linearity
[en] Integral Non Linearity
[en] Test bench
|Discipline(s) :||Engineering, computing & technology > Electrical & electronics engineering|
|Target public :||Researchers|
Professionals of domain
|Institution(s) :||Université de Liège, Liège, Belgique|
Deltatec, Liège, Belgique
|Degree:||Master : ingénieur civil électricien, à finalité spécialisée en "electronic systems and devices"|
|Faculty:||Master thesis of the Faculté des Sciences appliquées|
[en] High-Performance cameras are being used in an increasing number of applications. It requires designs that are more and more challenging. In order to validate these camera designs, a reusable automated test setup has been implemented to characterize the static performances of an image acquisition chain. This automated test setup features the characterization of the input referred noise, the integral non linarity (INL), the differential non linearity (DNL), the gain error, the offset error and the total unadjusted error (TUE) of the chain. By collecting samples out of the acquisition chains to build histograms, the static parameters can be computed.
By using samples associated to a DC level applied to the acquisition chain and by computing
the standard deviation of the built histogram, the input referred noise is computed.
Based on coherent sampling condition, a sine signal is applied to the acquisition chain. The collected samples allow to build a sine histogram that can be compared with an ideal sine histogram in order to compute the TUE, the INL, the DNL, the gain and the offset error.
In order to validate the measurement methods, a custom PCB has been designed. The PCB
features the acquisition chains to test, as well as a FPGA and a USB interface to collect data on
an external computer. After having programmed the FPGA to interface with the acquisition chain
and the USB port, samples can be collected. A remote control of the signal sources (DC and sine
generator) has also been implemented using a VISA interface to ease the acquisition and automate the test process.
From the collected samples the static performances of the acquisition chain can be computed.
The computation is done in post processing on a computer. From these computed performances,
the test protocol can be validated. Most of the obtained results are already promising since they
are coherent with the theoretical ones, even if improvements can still be brought to them.
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