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Faculté des Sciences appliquées
Faculté des Sciences appliquées
MASTER THESIS
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Master thesis : DisplayPort - Auxiliary channel monitoring and main link optimization for ProAV applications

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Navez, Pierre ULiège
Promotor(s) : Redouté, Jean-Michel ULiège
Date of defense : 28-Jan-2022 • Permalink : http://hdl.handle.net/2268.2/13876
Details
Title : Master thesis : DisplayPort - Auxiliary channel monitoring and main link optimization for ProAV applications
Author : Navez, Pierre ULiège
Date of defense  : 28-Jan-2022
Advisor(s) : Redouté, Jean-Michel ULiège
Committee's member(s) : Vanderbemden, Philippe ULiège
Laurent, Philippe ULiège
Language : English
Discipline(s) : Engineering, computing & technology > Electrical & electronics engineering
Institution(s) : Université de Liège, Liège, Belgique
Degree: Master : ingénieur civil électricien, à finalité spécialisée en "electronic systems and devices"
Faculty: Master thesis of the Faculté des Sciences appliquées

Abstract

[en] Upon the establishment of a DisplayPort connection between a source and a sink device, the two entities perform a link training. Link training is a communication that occurs on an auxiliary channel which aims at determining the configuration of the main link.

Indeed, the main link is composed of four differential lanes for which the voltage swing and pre-emphasis levels are adapted depending on the channel quality and the source and sink capabilities, for optimizing the data transmission.

High-bandwidth digital signal such as those carried by DisplayPort main link lanes suffer from degradation due to PCB traces or due to the signal attenuation in long cables. However, a redriver can be put on the path of the main link lanes to equalize the digital signals and apply a gain to counteract these losses. The gains applied in the redriver channels should take the outcome of the link training into account.

For a video playout module equipped with a DisplayPort interface developed by Deltacast.TV for the ProAV market, the settings of the redriver mounted on its PCB are not adapted depending on the link training results.

This thesis proposes an FPGA-based embedded system that combines: an hardware level capable of decoding and interpreting the data exchanged on the DisplayPort auxiliary channel during the link training, and a software level including a softcore processor responsible to dynamically configure a redriver placed on the path of the DisplayPort main link.


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Author

  • Navez, Pierre ULiège Université de Liège > Master ingé. civ. électr., à fin.

Promotor(s)

Committee's member(s)

  • Vanderbemden, Philippe ULiège Université de Liège - ULiège > Dép. d'électric., électron. et informat. (Inst.Montefiore) > Capteurs et systèmes de mesures électriques
    ORBi View his publications on ORBi
  • Laurent, Philippe ULiège Université de Liège - ULiège > Dép. d'électric., électron. et informat. (Inst.Montefiore) > Systèmes microélectroniques intégrés
    ORBi View his publications on ORBi
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