Electrical performance of electrostatically doped channels for future gate-all-around transistors

Abstract

For many years, the main challenge in the transistor technology is their scaling. To overcome this problem, new technologies, materials and architectures are introduced. One possibility could be the use of an ultra-thin electrostatically doped Silicon layer as channel for gate-all-around transistors. The Silicon layer is modeled by a Silicon-On-Insulator capacitor. The thesis is divided in two main parts. The first part will examine theoretically the electrical performance by using the Sentaurus simulation software. The second part will study the electrical performance through the resistivity characterized by the sheet resistance. In the first part of this work, a first and well-known capacitor is theoretically studied. Then, the complexity of the capacitor is gradually increased to finish with the SOI capacitor. The charge carrier densities are studied in the different structures for a variation of the back-gate voltage. From this, for different thin Silicon thicknesses, the electrical performance of this electrostatically doped layer is deduced. Indeed, the thinner the layer, the higher charge carriers density is at the Silicon surface. In the second part of this work, the electrical performance is studied through the sheet resistance. Indeed, the sheet resistance of the ultra-thin Silicon layer is measured with the micro-four-point probe method. Several parameters will vary to find the best combination to have the more accurate measurements. Then, the effect of the back-gate voltage on the sheet resistance is analysed. Obtaining accurate measurements on a ultra-thin doped layer is difficult, even impossible. Knowing the electrical performance in theory, it could be due to the ultra-thin layer.