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Faculté des Sciences appliquées
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Master thesis : FPGA-based Shallow Packet Inspection for Diagnostics in 100GbE Networks

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Dupont, Xavier ULiège
Promotor(s) : Redouté, Jean-Michel ULiège
Date of defense : 4-Sep-2023/5-Sep-2023 • Permalink : http://hdl.handle.net/2268.2/18383
Details
Title : Master thesis : FPGA-based Shallow Packet Inspection for Diagnostics in 100GbE Networks
Translated title : [fr] Inspection des paquet superficielle basé sur FPGA pour le diagnostique de réseaux 100GbE
Author : Dupont, Xavier ULiège
Date of defense  : 4-Sep-2023/5-Sep-2023
Advisor(s) : Redouté, Jean-Michel ULiège
Committee's member(s) : Leduc, Guy ULiège
Mathy, Laurent ULiège
Language : English
Number of pages : 40
Keywords : [en] fpga
[en] verification methodology
[en] diagnostics
[en] near real-time
Discipline(s) : Engineering, computing & technology > Computer science
Institution(s) : Université de Liège, Liège, Belgique
Degree: Master en sciences informatiques, à finalité spécialisée en "computer systems security"
Faculty: Master thesis of the Faculté des Sciences appliquées

Abstract

[en] The requirements for achieving modern live broadcast production are immense. In order
to meet them, traditional computers and even business-grade servers are simply not enough or
unfit for the task in a world pushing more and more for ecology. The answer to this conundrum:
Field Programmable Gate Arrays (FPGA). These highly specialized devices can be programmed
to do the hard work: encoding and decoding video, process network traffic both incoming and
outgoing at speeds of up to 100GbE, in near real-time at a fraction of the energy consumption.
With these kinds of constraints, it is important everything goes according to plan, as a small
mistake in configuration can make a great night spent watching your favorite sport live in 4K,
become frustrating for millions of would-be watchers.
My task, then, was to create a design which would bring diagnostics information from FPGA-
land with the same constraints all the way up to the application layer running on a traditional
CPU. To that end, I creates various modules, each with its own role: the decoder analyzes the
network traffic passing through the FPGA and extract information out of it. From this data, a
CAM is used to assign an index to each packet such that packets of the same video/audio/ancil-
lary stream gets a unique identifier, allowing to distinguish and detect what exactly is happening
on the wire and pinpoint the problem. Additionally, another module keeps track of the activity
of all the streams, allowing to tell if any have timed out. A module called the Flow Store is
then used to relay that information to the application layer by handling the communication with
a CPU. Finally, the main module, called IP Analyzer, ensures these behave well together, by
synchronizing their operation.
A large part of this project is also a test to the robustness of my academic education as
my background in Computer Science is not necessarily favorable to a project in the domain of
electronics. Still, I was able to find a foothold relatively easily as I was also tasked with created
a comprehensive verification methodology in the likes of Universal Model Verification which I
have deemed Deferred Verification through Event Logging, or DeVEL. This method boasts the
advantage of being much more user-friendly, faster to deploy and overall more practical than its
standard counterpart at the cost of allowing parts of the testbench to be implemented freely by
the user which is a problem for code reuse and scaling.
Ultimately, my design, extensively tested with my own testbench implementation, is running
without a hitch on an actual server.


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Description: Thesis report
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Format: Adobe PDF

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Access Thesis.zip
Description: Project
Size: 94.98 MB
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Author

  • Dupont, Xavier ULiège Université de Liège > Master sc. informatiques, à fin.

Promotor(s)

Committee's member(s)

  • Leduc, Guy ULiège Université de Liège - ULiège > Dép. d'électric., électron. et informat. (Inst.Montefiore) > Réseaux informatiques
    ORBi View his publications on ORBi
  • Mathy, Laurent ULiège Université de Liège - ULiège > Dép. d'électric., électron. et informat. (Inst.Montefiore) > Systèmes informatiques répartis et sécurité
    ORBi View his publications on ORBi
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