Master thesis : Implementing pipelining for an FPGA incarnation of the beta machine

Abstract

Computers have become an essential tool in our daily lives, playing an increasingly important role. They are present in various forms such as telephones, watches, robotics, and embedded systems, all of which contain processors that are becoming more powerful over time.

This thesis explores low-level computing and delves into how processors work by examining one of the solutions used by processor designers to improve performance: Pipelining. In order to accomplish this task, we will use the DE10-Nano development board that contains an FPGA. We will then program the FPGA with a Beta machine, which can be viewed as a simplified 32-bit processor. This machine is introduced in the Computation structures course at ULiège. Previously, Quentin Polet developed an FPGA version of this Beta machine during his master's thesis.

The implementation of pipelining in the CPU of this Beta machine reveals two significant issues with this technique: data and control hazards. These issues will be addressed and resolved in a new version of the Beta machine. The new version will process the same programs much faster than its predecessor, demonstrating the effectiveness of pipelining in enhancing processor performance.