Measurements Analytics In SRv6 Segment
Baguette, Brice
Promoteur(s) : Leduc, Guy
Date de soutenance : 5-sep-2024/6-sep-2024 • URL permanente : http://hdl.handle.net/2268.2/21148
Détails
Titre : | Measurements Analytics In SRv6 Segment |
Auteur : | Baguette, Brice |
Date de soutenance : | 5-sep-2024/6-sep-2024 |
Promoteur(s) : | Leduc, Guy |
Membre(s) du jury : | tychon, Emmanuel
Donnet, Benoit Mathy, Laurent |
Langue : | Anglais |
Discipline(s) : | Ingénierie, informatique & technologie > Sciences informatiques |
Institution(s) : | Université de Liège, Liège, Belgique |
Diplôme : | Master en ingénieur civil en informatique, à finalité spécialisée en "intelligent systems" |
Faculté : | Mémoires de la Faculté des Sciences appliquées |
Résumé
[en] The increasing reliance on latency-sensitive applications such as video conferencing, online
gaming, and delay-based geolocation has made it crucial to ensure consistent and minimal
latency in international backbone networks. This thesis focuses on the development of a tool
to detect and analyze latency imbalances and other anomalies in SRv6 networks using network
measurements. The primary sources of latency imbalances are identified as architectural issues
in network design and hardware programming errors in routers.
The research begins with a comprehensive study of the transport domain and the IPv6
protocol, detailing the structure of packets and the routing algorithms employed including
IS-IS and Flex Algo. It will introduce as well the Dijkstra algorithm’s and ECMP for load
balancing. An emulation tool is implemented to simulate network traffic and evaluate latency
across different paths. The analysis reveals that improperly configured ECMP paths can lead
to significant variations in latency, adversely affecting network performance.
A novel algorithm for detecting hardware issues related to incorrect network interface pro-
gramming is proposed. This algorithm helps identify routers that cause increased latency due
to misprogrammed paths. The tool’s effectiveness is validated through extensive testing on
emulated networks, demonstrating its capability to detect and address both architectural and
hardware-related latency issues.
Finally, a graphical interface is developed to provide a user-friendly platform for network
operators to visualize and manage the detected anomalies. The interface integrates simulation,
topology analysis, and hardware issue detection functionalities, enhancing the overall utility of
the tool.
This work contributes to improving the reliability and performance of SRv6 networks by
providing a robust solution for latency imbalance detection and mitigation.
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