Master thesis : SMPTE ST 2110 Stream Analyzer

Abstract

The broadcast industry is transitioning from Serial Digital Interface, SDI, systems to an uncompressed IP-based architecture because of the necessity to have more flexibility and scalability of the networks. The SMPTE ST 2110 standards have emerged to guide this transition and define how uncompressed media, such as video, audio and ancillary data, is carried over an IP network.

While IP networks do offer multiple advantages, they come with their own challenges, specifically in terms of timing and network jitter as well as possible buffer congestion. Commercial analyzers for these streams do exist but they operate as black boxes and cannot be integrated into custom hardware. Thus, this thesis presents the design and implementation of an SMPTE ST 2110 stream analyzer implemented on an FPGA and developed at Deltatec.

The SMPTE ST 2110 stream analyzer uses a hardware and software co-design that allows the FPGA to monitor high-speed streams, with the visualization being done with a Python interface.

This analyzer is comprised of four modules. The Packet Interval Time, PIT, analyzer measures the difference in time between packet arrivals and outputs an animation of the minimum, maximum, and average over time, as well as a PIT histogram. The Virtual Receiver buffer, VRX, analyzer implements the SMPTE ST 2110-21 virtual receiver buffer and outputs the buffer level's minimum, maximum, and average over time to ensure that the buffer is not dealing with any overflows or underflows.

The Network Compatibility model, C, analyzer observes the sender's traffic shaping against the actual network compatibility model in order to ensure that Ethernet switch buffers do not overflow. The RTP stream analyzer monitors redundant streams to decide which receiver class they should belong to and whether the packets are coming too far out of order.