Efficient HDL high-level synthesis for FPGA-accelerated CPUs and case study of an image transform kernel

Abstract

This thesis consists of two relatively distinct works. In the first part, we improve the performance of an open-source medical image processing pipeline used for drug development through the use of an FPGA accelerator interfaced with the main processor. In the process, we identify the bottlenecks, study potential mathematical improvements to the internal algorithm and discuss highly parallel and pipelined approaches to be implemented in the FPGA.

The second part of this thesis introduces a research project (from Stanford University and EPFL) for automatic generation of high performance hardware implementations from specifically designed high-level languages, for targeting among other parallel circuits, FPGAs. The application from the first part of the thesis is used as a testing platform for this tool-chain by implementing the algorithm in the provided high-level language. The resulting hardware system is then analyzed from which potential improvements to the tool-chain (and in particular, the high-level language) are deduced and presented.