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Faculté des Sciences appliquées
Faculté des Sciences appliquées
MASTER THESIS
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Implementing the beta machine on a Terasic DE10 SoC + FPGA development board

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Polet, Quentin ULiège
Promotor(s) : Fontaine, Pascal ULiège ; Mathy, Laurent ULiège
Date of defense : 24-Jun-2021/25-Jun-2021 • Permalink : http://hdl.handle.net/2268.2/11612
Details
Title : Implementing the beta machine on a Terasic DE10 SoC + FPGA development board
Translated title : [fr] Mise en œuvre de la machine bêta sur une carte de développement Terasic DE10 SoC + FPGA
Author : Polet, Quentin ULiège
Date of defense  : 24-Jun-2021/25-Jun-2021
Advisor(s) : Fontaine, Pascal ULiège
Mathy, Laurent ULiège
Committee's member(s) : Boigelot, Bernard ULiège
Language : English
Number of pages : 94
Keywords : [en] FPGA
[en] Computer
[en] CPU
[en] Verilog
[en] Harvard
[en] ARM
[en] VESA
[en] Avalon
Discipline(s) : Engineering, computing & technology > Electrical & electronics engineering
Institution(s) : Université de Liège, Liège, Belgique
Degree: Master : ingénieur civil électricien, à finalité spécialisée en "electronic systems and devices"
Faculty: Master thesis of the Faculté des Sciences appliquées

Abstract

[en] Implementing the Beta machine on a FPGA+SoC board (Terasic DE-10 NANO) to provide a lab platform to students of the course "Computation Structures INFO0012-2, ULiège".


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Author

  • Polet, Quentin ULiège Université de Liège > Master ingé. civ. électr., à fin.

Promotor(s)

Committee's member(s)

  • Boigelot, Bernard ULiège Université de Liège - ULiège > Dép. d'électric., électron. et informat. (Inst.Montefiore) > Informatique
    ORBi View his publications on ORBi
  • Total number of views 46
  • Total number of downloads 400










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