Master Thesis Online
Implementing the beta machine on a Terasic DE10 SoC + FPGA development board
Polet, Quentin 
Promotor(s) :
Fontaine, Pascal
;
Mathy, Laurent
Date of defense : 24-Jun-2021/25-Jun-2021 • Permalink : http://hdl.handle.net/2268.2/11612
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| Title : | Implementing the beta machine on a Terasic DE10 SoC + FPGA development board |
| Translated title : | [fr] Mise en œuvre de la machine bêta sur une carte de développement Terasic DE10 SoC + FPGA |
| Author : | Polet, Quentin
|
| Date of defense : | 24-Jun-2021/25-Jun-2021 |
| Advisor(s) : | Fontaine, Pascal
Mathy, Laurent
|
| Committee's member(s) : | Boigelot, Bernard
|
| Language : | English |
| Number of pages : | 94 |
| Keywords : | [en] FPGA [en] Computer [en] CPU [en] Verilog [en] Harvard [en] ARM [en] VESA [en] Avalon |
| Discipline(s) : | Engineering, computing & technology > Electrical & electronics engineering |
| Institution(s) : | Université de Liège, Liège, Belgique |
| Degree: | Master : ingénieur civil électricien, à finalité spécialisée en "electronic systems and devices" |
| Faculty: | Master thesis of the Faculté des Sciences appliquées |
Abstract
[en] Implementing the Beta machine on a FPGA+SoC board (Terasic DE-10 NANO) to provide a lab platform to students of the course "Computation Structures INFO0012-2, ULiège".
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Implementing the beta machine on a Terasic DE10 SoC + FPGA development board.pdf
Description: Report of the master thesis
Size: 2.57 MB
Format: Adobe PDF
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